## FEC 功能解决什么问题
FEC（前向纠错）的核心目标是提高数据传输的可靠性：
**解决的问题：**
- 在噪声干扰的物理信道中，数据传输容易出错
- 通过在发送端添加冗余校验信息，让接收端能够检测和纠正传输错误
- 降低误码率，确保数据传输质量
**带来的代价：**
- **延时增加**：编码和解码过程需要时间
- **带宽消耗**：冗余信息占用额外带宽
## 以太网 10GBASE-R FEC 处理的过程介绍
### 发送侧
处理流程始于从 PCS 接收连续的 64B/66B 码块。每个 66B 码块包含 2 比特的同步头（Sync Header）和 64 比特的载荷。同步头的值固定为 01（数据块）或 10（控制块）。BASE-R FEC 的第一个关键创新在于同步头压缩 1 。它利用了同步头两位比特始终相反的特性（一位是另一位的取反），仅保留第二位比特，并将其作为 转码比特（Transcode bit, T-bit）。第一位比特则被丢弃。通过这种方式，每个 66B 码块被转换为一个 65 比特的字，从而为 FEC 校验位腾出了宝贵的带宽，每 32 个 66B 码块就能节省出 32 比特。
为了进一步保证传输信号的直流平衡和频谱特性，标准规定了一个额外的扰码步骤。生成的 T-bit 需要与对应 64B 码块载荷中的第 8 个比特（data bit 8）进行异或（XOR）操作 。可以打破 T-bit 可能出现的长连 0或长连1序列
经过上述处理后，32 个 65 比特的字被聚合成一个 2080 比特的消息块。接着，(2112,2080) 循环码编码器对这个 2080 比特的消息块进行计算，生成 32 比特的奇偶校验位。
将生成的 32 比特校验位附加到 2080 比特的消息块之后，形成一个完整的 2112 比特 FEC 块。
为了确保整个 FEC 块在信道上传输时DC均衡，整个 2112 比特的 FEC 块还需要经过一个伪随机序列（PN-2112）扰码器的处理，然后才被送往 PMA 子层进行串行化和发送。
接收侧：
BASE-R FEC 的接收端面临一个独特的挑战：它没有像 RS-FEC 那样的显式对齐标记来辅助同步。因此，其同步过程依赖于 FEC 自身的纠错特性，采用一种试错（trial-and-error）机制 。
接收端首先对收到的串行比特流进行 PN-2112 解扰。然后，它在一个滑动窗口内不断尝试对 2112 比特的数据进行 FEC 解码和校验。具体来说，接收端会假设一个 FEC 块的起始位置，对该位置开始的 2112 比特进行校验计算。如果计算出的校验位与接收到的校验位不匹配，则说明同步位置错误，接收端会将窗口向后滑动一个比特位，然后重复尝试。这个过程被称为比特滑动（slip）。
当接收端在某个对齐位置上连续成功解码了 n 个 FEC 块（标准规定 n=4）时，就宣告 FEC 块锁定（fec_block_lock），同步成功 。此后，接收端就按此边界对后续数据进行解码和纠错。如果在锁定状态下，连续出现m 个解码失败的块（标准规定 m=8），则认为同步失锁。
后续的过程就是和发送测相反的一个过程。
优点：
在不增加带宽的情况下增加了FEC功能
---**Figure Title:**
Figure 74-6—FEC Transmit bit ordering
**Inputs (Top):**
- FEC:IS\_UNITDATA.request(tx\_bit) for 40GBASE-R and 100GBASE-R
- FEC:IS\_UNITDATA.request(tx\_bit) for 25GBASE-R (from PCS/PMA)
- A block labeled with tick marks and bit indices 0 through 15, labeled "tx\_data-group<0> tx\_data-group<15> (from PCS for 10GBASE-R)"
**Processing Blocks and Flow:**
1. Input feeds into a block labeled "Reverse Gearbox function".
2. Output of "Reverse Gearbox function" feeds into two places:
- A register-like block labeled "64B/66B output of PCS function". This block is segmented and labeled S0, S1, S2, S3, S4, S5, S6, S7. Each S segment appears to contain 8 bits (0 to 7). The first two bits are labeled 0 and 1, with bit 0 labeled "Sync header".
- It also feeds directly into the "64B/66B to 65b Transcoder" block.
3. The "64B/66B output of PCS function" block also feeds into the "64B/66B to 65b Transcoder" block.
4. An annotation points from bit 1 of the "64B/66B output of PCS function" block to a point near the input of the Transcoder block, labeled "Transcode bit T = SH.1 XOR S1.0". (SH.1 refers to bit 1 of the Sync Header, S1.0 refers to bit 0 of S1).
5. Output of the "64B/66B to 65b Transcoder" block is labeled "Output of Transcoder function". This output feeds into a second register-like block, also segmented S0 through S7 with 8 bits each (0 to 7), preceded by a single bit labeled 0. The first bit (labeled 0) is also pointed to by the "Transcode bit T = SH.1 XOR S1.0" annotation. This output feeds into the "FEC (2112,2080) Encoder" block.
6. The "FEC (2112,2080) Encoder" block is described as "Aggregate 32 65b blocks plus 32b Parity".
7. The output of the "FEC (2112,2080) Encoder" is depicted as a conceptual block structure labeled "FEC block". This block contains:
- "65b Block 0" with bit indices 0 to 64.
- "65b Block 1" with bit indices 0 to 64.
- ... (indicated by a dashed line)
- "65b Block 31" with bit indices 0 to 64.
- "32b Parity₃₁" with bit indices 0 to 31.
8. The "FEC block" concept feeds into the "PN-2112 Scrambler" block.
9. The output of the "PN-2112 Scrambler" feeds into a block labeled with tick marks and bit indices 0 through 15, labeled "tx\_data-group<0> tx\_data-group<15>".
**Outputs (Bottom):**
- The final "tx\_data-group<0> tx\_data-group<15>" block feeds into two outputs:
- PMA:IS\_UNITDATA.request(tx\_bit) for 40GBASE-R and 100GBASE-R
- PMA:IS\_UNITDATA.request(tx\_bit) for 25GBASE-R (to PMA)
**Textual Information:**
* **Figure Title:** Figure 74–10—FEC Receive bit ordering
* **Labels/Annotations:**
* FEC:IS\_UNITDATA\_i.request(rx\_bit) (to PCS/PMA for 40GBASE-R and 100GBASE-R)
* FEC:IS\_UNITDATA.request(rx\_bit) (to PCS/PMA for 25GBASE-R)
* tx\_data-group<0> tx\_data-group<15> (to PCS for 10GBASE-R)
* Sync header
* 64B/66B blocks to PCS function
* SH.0 SH.1
* Reconstruct 65b to 64B/66b blocks
* Descrambled Transcode bit T
* Descramble Transcode bit T = Received Transcode bit XOR S1.0
* 65b Blocks
* Received Transcode bit S1.0
* FEC (2112,2080) Decoder and Error correction (32 65b Blocks)
* FEC block
* 65b Block 0
* 65b Block 1
* ...
* 65b Block 31
* 32b Parity
* PN-2112 Descrambler and FEC block Sync
* tx\_data-group<0> tx\_data-group<15> (from PMA for 10GBASE-R)
* PMA:IS\_UNITDATA\_i.request(rx\_bit) (from PMA for 40GBASE-R and 100GBASE-R)
* PMA:IS\_UNITDATA.request(rx\_bit) (from PMA for 25GBASE-R)
* **Labels on data blocks:**
* S0 S1 S2 S3 S4 S5 S6 S7 (appears multiple times, indicating segments within blocks)
* Bit indices: 0, 1, ... 7 (under S0-S7)
* Bit indices: 0, ... 64 (under 65b Blocks 0, 1, ..., 31)
* Bit indices: 0, ... 31 (under 32b Parity)
* Bit indices: 0, ... 15 (under tx\_data-group boxes)
* Bit indices: 0, 1 (under Sync header SH.0 SH.1)
**Chart/Diagram Description:**
* **Type:** Block diagram / Flowchart showing data processing steps.
* **Main Elements:**
* **Boxes:** Represent processing functions or stages:
* "Reconstruct 65b to 64B/66b blocks"
* "Descramble Transcode bit T = Received Transcode bit XOR S1.0"
* "FEC (2112,2080) Decoder and Error correction (32 65b Blocks)"
* "PN-2112 Descrambler and FEC block Sync"
* **Rectangular Blocks (representing data):**
* Blocks labeled S0 through S7 (each with bits 0-7) appearing in multiple stages.
* Blocks labeled "65b Block 0" through "65b Block 31" (each with bits 0-64).
* Block labeled "32b Parity" (with bits 0-31).
* Small block labeled "Sync header" with sub-blocks SH.0 and SH.1 (each with bits 0,1).
* Blocks representing data groups tx\_data-group<0> to tx\_data-group<15> (each with bits 0-15) at the input and output.
* **Lines/Arrows:** Indicate the direction of data flow between blocks and stages. Lines connect data blocks to processing boxes and output blocks to other systems.
* **Labels and Annotations:** Textual labels describe the type of data blocks (e.g., "64B/66B blocks", "Descrambled Transcode bit T", "65b Blocks", "FEC block") and the destination/source of data streams (e.g., "to PCS/PMA for ...", "from PMA for ..."). Specific bits or segments (like S1.0 or the indices 0-64) are also labeled.
* **Relative Position and Direction:** The diagram shows a top-to-bottom flow, indicating processing steps. Data enters from the bottom (from PMA), goes through descrambling and decoding, forms FEC blocks, and then outputs (to PCS/PMA). A side path shows the generation of "Descrambled Transcode bit T" from "Received Transcode bit" and S1.0. The sync header is extracted early in the process.