------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date: 13:45:14 05/22/2022 -- Design Name: -- Module Name: Sram - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use IEEE.STD_LOGIC_ARITH.ALL;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity Sram is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; DATA : inout STD_LOGIC_VECTOR (15 downto 0); ADDR : out STD_LOGIC_VECTOR (15 downto 0); Input_data : in STD_LOGIC_VECTOR (15 downto 0); RAM1_EN : out STD_LOGIC;--片选信号 RAM1使能 RAM1_OE : out STD_LOGIC;--读信号 输出使能 RAM1_WE : out STD_LOGIC;--写信号 写使能 ctrl_r : in STD_LOGIC; dbc : out STD_LOGIC; LIGHT : out STD_LOGIC_VECTOR (15 downto 0); stateCnt: out STD_LOGIC_VECTOR (6 downto 0);--对应七段数码管); stateCnt2: out STD_LOGIC_VECTOR (6 downto 0));--对应七段数码管);end Sram;architecture Behavioral of Sram is signal tmp_addr:STD_LOGIC_VECTOR (15 downto 0):=x"0000"; --X代表16进制:X"0000"等于"0000000000000000" signal tmp_read_addr:STD_LOGIC_VECTOR (15 downto 0):=x"0000"; signal tmp_data:STD_LOGIC_VECTOR (15 downto 0):=x"0000"; signal tmp_read_data:STD_LOGIC_VECTOR (15 downto 0):=x"0000"; signal to_light:STD_LOGIC_VECTOR (15 downto 0):=x"0000"; type sram_state is(prepare,start,achieve,waiting,over);--枚举类型 定义SRAM状态 写状态 --type read_sram_state is (waiting,start,reading,over);--读取状态 type prj_state is(r,w,n);--枚举类型 signal ctrl_state:prj_state;--枚举类型赋给ctrl_state signal write_state,read_state:sram_state; --signal read_state:read_sram_state; signal state_controler:std_logic_vector(1 downto 0):="00";beginprocess(RST,ctrl_r) begin if RST='0' then ctrl_state <=N; --仅当重置时状态才为N stateCnt2 <= not "0000000"; elsif rising_edge(ctrl_r) then case ctrl_state is when N => stateCnt2 <= not "1111001"; ctrl_state<=W; --重置后开始先写入 when W => stateCnt2 <= not "0100100"; ctrl_state<=R; --写后开始读 when R => stateCnt2 <= not "1111001"; ctrl_state<=W; --读完再写 end case; end if;end process;process(RST,CLK,ctrl_state) begin if RST='0' then --重置 tmp_data <=x"0000"; tmp_read_addr <=x"0000"; tmp_addr <=x"0000"; --x表示八进制（应该是十六进制） to_light <=x"0000"; RAM1_EN <= '1'; --RAM1的片选信号1未选中 RAM1_OE <= '0'; --读信号 RAM1_WE <= '0'; --写信号 write_state <= waiting; read_state <= waiting; stateCnt <= not "0000000"; elsif rising_edge(CLK) then --clk上升沿 case ctrl_state is when N => --仅当重置时状态才为N，当重置时不需有任何其他操作 when W => case write_state is when waiting => --0 write_state <= prepare; read_state <=waiting; tmp_addr <= INPUT_data; stateCnt <= not"1000000"; when prepare => --1 tmp_data<=Input_data; RAM1_EN <= '0'; RAM1_OE <= '1'; RAM1_WE <= '1'; ADDR <= tmp_addr; DATA <= tmp_data; write_state <= start; stateCnt <= not"1111001"; when start => --2 ADDR <= tmp_addr; DATA <= tmp_data; RAM1_WE<='0'; RAM1_OE<='1'; write_state <= achieve; stateCnt <= not"0100100"; when achieve=> --3 RAM1_OE<='1'; RAM1_WE<='0'; to_light<=DATA; write_state<=over; stateCnt <= not"0110000"; when over=> --4 write_state<=waiting; tmp_addr<=tmp_addr + 1; stateCnt <= not"0011001"; end case; when R=> case read_state is when waiting => --0 read_state<=prepare; write_state<=waiting; stateCnt <= not"1000000"; when prepare=> --1 tmp_read_addr<=Input_data;--输入读取的地址位置 RAM1_EN<='0'; RAM1_OE<='1'; RAM1_WE<='1'; ADDR<=tmp_read_addr; DATA<=(others=>'Z'); read_state<=start; stateCnt <= not"1111001"; when start=> --2 RAM1_OE<='0'; RAM1_WE<='1'; ADDR<=tmp_read_addr; read_state<=achieve; stateCnt <= not"0100100"; when achieve=> --3 RAM1_OE<='0'; RAM1_WE<='1'; to_light<=DATA; read_state<=over; stateCnt <= not"0110000"; when over=> --4 read_state<=waiting; tmp_read_addr<=tmp_read_addr + 1; stateCnt <= not"0011001"; end case; end case; end if; dbc<='1'; end process; light<=to_light;end Behavioral;讲解这段代码