帮我解答这一题---**Question Stem:** Figure 1 is the circuit diagram of a discrete-component amplifier designed by a student to amplify a weak signal of interest vsig(t) in the presence of a dominating unwanted component vunw(t) contributed by a distance source. The values of β for transistors Q1, Q2 and Q3 are 200, 200 and 300 respectively. **Circuit Diagram Description:** * **Type:** Circuit diagram. * **Title:** Figure 1: Circuit for Question 1 * **Components:** * **Power Supplies:** +15V terminal, -15V terminal. * **Input Sources:** AC voltage source v1 (connected to ground), AC voltage source v2 (connected to ground), DC current source Idc (1mA, pointing downwards). * **Transistors:** Q1 (NPN BJT), Q2 (NPN BJT), Q3 (NPN BJT). * **Resistors:** Rc1, Rc2, REB, R5 (3.0kohm), RL (1.0kohm). * **Capacitor:** C1 (1.0uF). * **Output:** Vo(t) voltage measured across RL (+ terminal at top of RL, - terminal at bottom of RL). * **Ground:** Connected to bottom terminal of v1, bottom terminal of v2, and bottom terminal of RL/C1. * **Connections and Topology:** * Differential amplifier input stage formed by Q1 and Q2. Bases connected to v1 and v2 respectively. Emitters are connected together. * Common emitters of Q1 and Q2 are connected to one end of resistor REB and the positive terminal of the DC current source Idc. * Negative terminal of Idc and the other end of REB are connected to the -15V supply. * Collectors of Q1 and Q2 are connected to resistors Rc1 and Rc2 respectively, which are connected to the +15V supply. * Collectors of Q1 and Q2 are also connected together at a common node. This node is connected to the base of transistor Q3. * Transistor Q3 acts as an output stage. Its collector is connected to the +15V supply. * Emitter of Q3 is connected to one end of resistor R5 (3.0kohm). * The other end of R5 is connected to one end of resistor RL (1.0kohm) and one end of capacitor C1 (1.0uF). * The other ends of RL and C1 are connected to ground. * The output voltage Vo(t) is across RL. * **Labels and Values:** * Idc: 1mA * R5: 3.0kohm * RL: 1.0kohm * C1: 1.0uF * β (Q1): 200 * β (Q2): 200 * β (Q3): 300 * Power Supply Voltages: +15V, -15V. * Signals: v1, v2, Vo(t), vsig(t), vunw(t). (Note: vsig(t) and vunw(t) are mentioned in the text as the signal of interest and unwanted component, likely related to v1 and v2, but the direct mapping is not explicitly given in the diagram). Here is the extracted text from the image: (a) Assuming that R_C1 = R_C2 = 10 kΩ, and the internal resistance REB of the current source is infinite, calculate DC bias points (Q-points) for all the transistors in Figure 1. Classify the region of operation of each transistor as active, cut-off or saturation. Will your classification change if REB = 470 kΩ? You should state and justify any assumptions that you make. (b) Draw the mid-band small signal equivalent circuit of the common-collector stage (Q3), taking the load RL into account. Derive symbolic expressions for the input impedance Zin and the voltage gain Av of the common collector (CC) stage. Substitute values for circuit components as given in Figure 1 and calculate numerical figures for Zin and Av. (c) Draw the differential mode half circuit of the amplifier in Figure 1, and derive an expression for the differential mode voltage gain (A_vds) of the differential amplifier stage, i.e., gain from the differential-mode input to the collector of Q2. The loading effect from the amplifier formed by Q3 should be taken into account. Rc1 = Rc2 = 10 kΩ and REB = 470 kΩ. Calculate A_vds. (d) The common-mode voltage gain from the common-mode input to the collector of Q2 has been calculated to be A_vcm = -0.01. The two components v_sig(t) and v_unw(t) appear at the two inputs v1(t) and v2(t) of the amplifier as described by Eq. (1) and (2): v1(t) = v_sig(t) + v_unw(t) (1) v2(t) = 0.01 v_sig(t) + 0.99 v_unw(t) (2) Write an expression for the voltage at the collector of Q2, when signals v1(t) and v2(t) are applied as shown in Figure 1. Has the amplifier succeeded in selectively amplifying the signal of interest v_sig(t)?